1. Field of the Invention
This invention generally relates to a semiconductor package, and more specifically, to a heat-dissipating structure and a heat-dissipating semiconductor package having the heat-dissipating structure.
2. Description of Related Art
A flip chip ball grid array (FCBGA) semiconductor package is a package structure that has a flip chip and a ball grid array for an active surface of a semiconductor chip to be electrically connected to one surface of a substrate via a plurality of conductive bumps, and also has a plurality of solder balls that serve as input/output terminals formed on the other surface of the substrate. Such package structure has significantly reduced package size, and eliminates the conventional wire design, thereby reducing impedance and enhancing electrical performance to avoid signal failing during the transmission process. Therefore, the FCBGA semiconductor package has become the main stream of the next generation packaging technology of the chips and the electronic elements.
Due to the advantageous features, the flip chip ball grid array package is mostly applied in the electronic elements of high integration to provide the desired package size and electrical performance for the electronic elements. However, such electronic elements produce more heat than general packages in the operation process due to high frequency of operation. Hence, the heat dissipation efficiency is an important key that affects the quality and the yield of the packaging technology.
In the conventional flip chip ball grid array semiconductor package, a heat sink is directly bonded to the non-active surface of the chip without encapsulant filled between the non-active surface and heat sink which has poor heat conductivity, so as to achieve a better heat dissipation efficiency.
Generally, the bonding material used for bonding the heat sink to the non-active surface of the flip chip semiconductor chip is epoxy-based, and has the heat conductivity coefficient of 2˜4 w/m° K. However, compared with the heat sink that has heat conductivity coefficient of hundreds w/m° K (for example, the heat conductivity coefficient of copper is 400 w/m° K), the epoxy-based bonding material can not dissipate heat effectively. Therefore, along with the demands of the electronic products or the semiconductor package elements for heat dissipation getting higher, it must be a trend to apply a higher heat conductivity coefficient bonding material for providing a better heat dissipation between the heat sink and the chip.
In view of the aforementioned reasons, U.S. Pat. Nos. 6,504,242, 6,380,621, and 6,504,723 use a tin-based (Sn-based) solder material as a thermal interface material (TIM) that bonds the heat sink and the flip chip semiconductor chip together. Since the solder material has the metal component, its heat conductivity coefficient is about 50 w/m° K, and if it is made of pure tin, its heat conductivity coefficient can be up to 86 w/m° K. Compared with the conventional epoxy-based bonding material, the Sn-based solder material has much higher heat conductivity capability, and therefore it is more capable of fitting the demands for heat dissipation.
Please refer to FIG. 1. However, such thermal interface material made of solder material 15 has great wetting capability with the heat sink 13 that is generally made of copper, such that as soon as the fusion process starts, the solder material 15 diffuses quickly on the heat sink 13. Thus the thickness formed is not sufficient to form a solder bonding between the heat sink 13 and the flip chip semiconductor chip 12; meanwhile, the bonding area between the solder material 15 and the flip chip semiconductor chip 12 is also reduced, thus causes breakage of solder material therebetween and affects heat dissipation efficiency and product reliability.
Please refer to FIG. 2, which is a cross-section view showing a flip chip semiconductor chip disclosed in U.S. Pat. No. 6,380,621. The metal layers 24 made of, for example nickel (Ni) or gold (Au), are preformed on the surface of the heat sink 23 and the non-active surface of the flip chip semiconductor chip 22, such that when the fusion process is performed on a thermal interface material, such as a solder material 25, the solder material 25 can have solder bonding with the metal layers 24, and thus limits the wetting area. However, this technique requires preforming separate metal layers of nickel (Ni) or gold (Au) on the surface of the heat sink and the non-active surface of the flip chip semiconductor chip, and therefore the fabrication process is complicated and the product cost is high as well.
Please refer to FIG. 3A and FIG. 3B, which are cross-section views showing a flip chip semiconductor chip disclosed in U.S. Pat. No. 6,504,723. A heat dissipation structure 33 is provided, and the heat dissipation structure 33 includes a raised section 331 that protrudes downward from the center of the heat dissipation structure 33 and then shrinks gradually, and an extension section 332 that extends downward from each side of the heat dissipation structure 33. The center raised section 331 has a flat bottom and four sloping surfaces, the surfaces of the raised section 331 has been preapplied with soldering flux 36, and then the heat dissipation structure 33 is pressed down via a bonding material 37 to a substrate 31 that has a flip chip semiconductor chip 32 mounted thereon. The raised section 331 of the heat dissipation structure 33 is pressed to the solder material 35 that is preapplied on the non-active surface of the flip chip semiconductor chip 32, and the fusion process is performed on the solder material 35, such that the solder material 35 disperses in the gap between the raised section 331 of the heat dissipation structure 33 and the flip chip semiconductor chip 32, and the solder material 35 is held by the sloping surfaces of the raised section 331 so as to restrict the flow thereof.
However, the heat-dissipating structure of U.S. Pat. No. 6,504,723 is too complicated and also has high production cost, it does not answer to the practical application and the economic consideration.
Hence, it is a highly urgent issue in the industry for how to provide a technique that has simple application and low production cost and is capable of restricting the solder thermal interface material to the wetting area between the heat sink and the semiconductor chip in order to prevent it from improper overflowing, meanwhile the technique is also capable of avoiding using a complicated heat-dissipating structure and eliminating the need of preapplying metal layers on the heat sink and the semiconductor chip, thereby giving the benefits of saving fabrication time and production cost.